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Publications by M. Pedram
Improving Sampling Efficiency for System Level Power Estimation
Analysis and Optimization of Ground Bounce in Digital CMOS Circuits
Layout Driven Logic Restructuring/Decomposition
Cell Delay Analysis Based on Rate-Of-Current Change
A New Design of Double Edge Triggered Flip-Flops
Accurate Prediction of Physical Design Characteristics for Random Logic
Reducing Transitions on Memory Buses Using Sector-Based Encoding Technique
Timing-Driven Bipartitioning With Replication Using Iterative Quadratic Programming
Parameterized Block-Based Non-Gaussian Statistical Gate Timing Analysis
A Simultaneous Routing Tree Construction and Fanout Optimization Algorithm
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