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Publications by Mateo Valero
Killer-Mobiles: The Way Towards Energy Efficient High Performance Computers?
Direct Inter-Process Communication (dIPC)
Architectural Support for Task Dependence Management With Flexible Software Scheduling
Runahead Threads to Improve SMT Performance
Proceedings - International Symposium on High-Performance Computer Architecture
Hardware
Engineering
Architecture
A Simple Low-Energy Instruction Wakeup Mechanism
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Toward Kilo-Instruction Processors
Transactions on Architecture and Code Optimization
Hardware
Information Systems
Architecture
Software
Dynamic Memory Interval Test vs. Interprocedural Pointer Analysis in Multimedia Applications
Transactions on Architecture and Code Optimization
Hardware
Information Systems
Architecture
Software
Optimising Long-Latency-Load-Aware Fetch Policies for SMT Processors
International Journal of High Performance Computing and Networking
Hardware
Computer Networks
Software
Architecture
Communications
A Latency-Conscious SMT Branch Prediction Architecture
International Journal of High Performance Computing and Networking
Hardware
Computer Networks
Software
Architecture
Communications
Increasing the Number of Strides for Conflict-Free Vector Access
ACM SIGARCH Computer Architecture News
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