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Publications by Narayanam Balaji

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture

International Journal of Intelligent Engineering and Systems

Computer Science

English

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Area-Delay Efficient Flipping 2-D DWT Structure Using PEB Booth Multiplier

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FPGA Implementation of Low Power Booth Multiplier Using Radix-4 Algorithm

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Hardware Efficient Multiplier-Less Multi-Level 2D DWT Architecture Without Off-Chip RAM

IET Image Processing

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Design of 2-D DWT VLSI Architecture for Image Compression

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A High-Efficient Line-Based Architecture for 2-D Lifting-Based DWT Using 9/7 Wavelet Filters

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Modified Booth Multiplier Using Wallace Structure and Efficient Carry Select Adder

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Implementation of Power Efficient Vedic Multiplier

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A High Speed 2-D DWT Architecture Using 9/7 Lifting Scheme for Image Compression

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CNTFET Based Highly Durable Radix-4 Multiplier Using an Efficient Hybrid Adder

Biosciences Biotechnology Research Asia

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