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Publications by S. Chacko
A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-Μm CMOS PLL Based on a Sample-Reset Loop Filter
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
Related publications
Low Power Low Jitter 0.18 CMOS Ring VCO Design With Strategy Based on EKV3.0 Model
International Journal of Advanced Computer Science and Applications
Computer Science
A 5V Charge Pump in a Standard 1.8-V 0.18-Μm CMOS Process
A Low Power 3-Stage Voltage-Controlled Ring Oscillator in 0.18 Μm CMOS Process for Active RFID Transponder
Elektronika ir Elektrotechnika
Electronic Engineering
Electrical
An On-Chip Antenna Integrated With a Transceiver in 0.18-Μm CMOS Technology
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Design of a Digital Modulator and Demodulator for Reader-Less RFID Tag in 0.18 Μm CMOS Process
Acta Scientiarum - Technology
Planetary Sciences
Astronomy
Engineering
Computer Science
Mathematics
Earth
Chemistry
Physics
A 3.3-mW ΣΔ Modulator for UMTS in 0.18-Μm CMOS With 70-dB Dynamic Range in 2-MHz Bandwidth
IEEE Journal of Solid-State Circuits
Electronic Engineering
Electrical
A Low Jitter Phase-Locked Loop Based on Self-Biased Techniques
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
A Compact Band Selection Filter in 0.18-^|^micro;m CMOS Technology
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Design of Frequency Discriminator for Ringer Using 0.18 Μm CMOS Technology
International Journal of Engineering and Technology
