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Publications by S. K. Manikandan
Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics With Bit Reduction Technique
Circuits and Systems
Related publications
Design of an Optimized High Speed Multiplier Using Vedic Mathematics
Contemporary Engineering Sciences
Materials Science
Mutagenesis
Computer Networks
Fluid Flow
Communications
Engineering
Health
Transfer Processes
Toxicology
Social Sciences
High Speed 32-Bit Vedic Multiplier for DSP Applications
International Journal of Computer Applications
Implementation of 24 Bit High Speed Floating Point Vedic Multiplier
International Journal of Advance Engineering and Research Development
Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier
International Journal of Electrical, Electronics and Computers
Implementation of Power Efficient Vedic Multiplier
International Journal of Computer Applications
Temperature Sensing Based Energy Efficient Vedic Multiplier Design Using Either Proportionality or Similarity
Gyancity Journal of Engineering and Technology
Implementation of 64 Bit Complex Floating-Point Multiplier on FPGA Using Vedic Mathematics Sutra- Urdhva Tiryagbhyam
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
Design of Vedic Multiplier Using SQRT Carry Select Adder (CSLA)
International Journal of MC Square Scientific Research
Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications
International Journal of Innovative Technology and Exploring Engineering
Mechanics of Materials
Electronic Engineering
Civil
Structural Engineering
Electrical
Computer Science
