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Publications by Sai Prasanth Muralidhara
Slicing Based Code Parallelization for Minimizing Inter-Processor Communication
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Inter-Processor and Inter-Process Communication in Realtime Multi-Process Computing
IFAC Proceedings Volumes
Duplicated Code Slicing Technique for System Optimization
International Journal of Recent Technology and Engineering
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Innovation
Parallelization of Gyrokinetic PIC Code for MHD Simulation
Progress in Nuclear Science and Technology
Minimizing Expected Makespans on Uniform Processor Systems
Advances in Applied Probability
Applied Mathematics
Statistics
Probability
A Post-Processor for the PEST Code
Energy-Aware Parallelization Flow and Toolset for C Code
Hierarchy-Based Algorithms for Minimizing Makespan Under Precedence and Communication Constraints
OFFSCALE: A PC Input Processor for the SCALE Code System. The CSASIN Processor for the Criticality Sequences
Subspace-Based Channel Estimation for Code Division Multiple Access Communication Systems
IEEE Transactions on Communications
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Electrical