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Publications by Shigeo Satoh
Neutron-Induced Soft-Error Simulation Technology for Logic Circuits
Related publications
Technology Mapping Algorithms for CMOS Dynamic Logic Circuits.
Robust Flip-Flop Against Soft Errors for Combinational and Sequential Logic Circuits
Iterative Remapping for Logic Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
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Computer Graphics
Computer-Aided Design
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Digital Logic for Soft Devices
Proceedings of the National Academy of Sciences of the United States of America
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Power Estimation Methods for Sequential Logic Circuits
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International Journal of Science and Research (IJSR)
Cascadable Adiabatic Logic Circuits for Low-Power Applications
IET Circuits, Devices and Systems
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Reliability Analysis of Logic Circuits
Microelectronics Reliability
Surfaces
Electronic Engineering
Condensed Matter Physics
Electronic
Molecular Physics,
Nanoscience
Films
Optical
Electrical
Atomic
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Reliability
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Coatings
Optics
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Risk
