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Publications by Sree NivasA
Implementation of Power Efficient Vedic Multiplier
International Journal of Computer Applications
Related publications
Implementation of Vedic Multiplier and Floating Point Matrix Multiplier in Image Compression Applications
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Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier
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Implementation of 24 Bit High Speed Floating Point Vedic Multiplier
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Design of an Efficient Binary Vedic Multiplier for High Speed Applications Using Vedic Mathematics With Bit Reduction Technique
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Temperature Sensing Based Energy Efficient Vedic Multiplier Design Using Either Proportionality or Similarity
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An Efficient Two’s Complement Multiplier With FPGA Implementation
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