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Publications by Y. Tosaka

Robust Flip-Flop Against Soft Errors for Combinational and Sequential Logic Circuits

2008English

Related publications

Mitigation of Soft Errors on 65NM Combinational Logic Gates via Buffer Gate

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"Flip Flop" Sandals.

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On the Use of Evolutionary Programming for Combinational Logic Circuits Design

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Power Estimation Methods for Sequential Logic Circuits

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Modeling and Mitigating Transient Errors in Logic Circuits

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Bilayer Defects Facilitate DPPC Flip-Flop

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A Simple Flip-Flop Circuit

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Detection and Masking of Trojan Circuits in Sequential Logic

Vestnik Tomskogo Gosudarstvennogo Universiteta - Upravlenie, Vychislitel'naya Tekhnika i Informatika
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Neutron-Induced Soft-Error Simulation Technology for Logic Circuits

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