Amanote Research
Register
Sign In
Bounded Dataflow Networks and Latency-Insensitive Circuits
doi 10.1109/memcod.2009.5185393
Full Text
Open PDF
Abstract
Available in
full text
Date
July 1, 2009
Authors
Muralidaran Vijayaraghavan
Publisher
IEEE
Related search
Quasi-Delay-Insensitive Circuits Are Turing-Complete
Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs
Monitor Circuits for LTL With Bounded and Unbounded Future
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Protecting Circuits From Leakage: The Computationally-Bounded and Noisy Cases
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Insensitive Call Admission Control for Wireless Multiservice Networks
IEEE Communications Letters
Electronic Engineering
Simulation
Computer Science Applications
Electrical
Modeling
Identifying Preferences in Networks With Bounded Degree
Econometrica
Economics
Econometrics
Bayesian Detection in Bounded Height Tree Networks
IEEE Transactions on Signal Processing
Electronic Engineering
Signal Processing
Electrical
Identifying Preferences in Networks With Bounded Degree
Dataflow Architectures and Multithreading
Computer
Computer Science
