On-Chip Decoupling Capacitor Optimization Using Architectural Level Prediction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - United States
doi 10.1109/tvlsi.2002.1043335
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

System Level Interconnect Design for Network-On-Chip Using Interconnect IPs

2003English

Research on the Cluster-Level Architectural Knowledge

International Journal of Knowledge and Systems Science
Information SystemsOrganizational BehaviorHuman Resource ManagementStrategyManagementInnovationManagement of TechnologyArtificial Intelligence
2012English

Networks-On-Chip Architecture Customization Using Network Partitioning: A System-Level Performance Evaluation

International Journal of Computing and Digital Systems
Computer GraphicsHuman-Computer InteractionComputer NetworksCommunicationsInformation SystemsComputer-Aided DesignInnovationManagement of TechnologyArtificial Intelligence
2015English

Optimization Models for Three On-Chip Network Problems

Transactions on Architecture and Code Optimization
HardwareInformation SystemsArchitectureSoftware
2016English

Level Crossing in Toroidal On-Chip Microcavities

2009English

On Decoupling Points and Decoupling Zones

Production and Manufacturing Research
IndustrialManufacturing Engineering
2014English

CVD Level Prediction Processor Using DNA Computing

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2009English

Burst-Level Congestion Control Using Hindsight Optimization

IEEE Transactions on Automatic Control
ControlSystems EngineeringComputer Science ApplicationsElectricalElectronic Engineering
2002English

An Architectural Approach to Level Design

The Computer Games Journal
2018English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy