Amanote Research
Register
Sign In
Multi-Step Binary-Weighted Capacitive Digital-To-Analog Converter Architecture
doi 10.1109/mwscas.2008.4616838
Full Text
Open PDF
Abstract
Available in
full text
Date
August 1, 2008
Authors
Ritu Raj Singh
Roman Genov
Ravi Teja Kotamraju
Baquer Mazhari
Publisher
IEEE
Related search
Settling Time Optimization Technique for Binary-Weighted Digital-To-Analog Converter
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Analog to Digital Converter
Analog-To-Digital Converter
An Analog-To-Digital Converter
Transactions of the I.R.E. Professional Group on Electronic Computers
A Novel Wavelet-Based Analog-To-Digital Converter
Compensation of Analog-To-Digital Converter Nonlinearities Using Dither
Periodica Polytechnica Electrical Engineering
An Integration-Type High Speed Analog-To-Digital Converter
A Digital Background Calibration Technique for Successive Approximation Register Analog-To-Digital Converter
Journal of Computer and Communications
Ultra Low Power Analog to Digital Converter for Biomedical Applications