Checkability of Fpga Projects by Power-Dissipation

Systems and Technologies
doi 10.32836/2521-6643-2018-1-56-5
Full Text
Abstract

Available in full text

Date
Authors
Publisher

University of Customs and Finance

Related search

Converter Power Losses Computation by FPGA-based HIL Simulator : Invited Paper

2019English

Estimation of Power Dissipation Using a Novel Power Macromodeling Technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ElectricalSoftwareComputer GraphicsComputer-Aided DesignElectronic Engineering
2000English

Estimating Power Dissipation in VLSI Circuits

IEEE Circuits and Devices Magazine
1994English

Low-Power FSMs in FPGA: Encoding Alternatives

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2002English

FSM Decomposition for Low Power in FPGA

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2002English

Design of Low Power Column Bypass Multiplier Using FPGA

IOSR journal of VLSI and Signal Processing
2012English

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

2017English

Calculation of RF Power Dissipation in Faraday Shield Tubes

AIP Conference Proceedings
AstronomyPhysics
1992English

Dynamic Power Reduction of FPGA-based Reconfigurable Computers Using Precomputation

ACM SIGARCH Computer Architecture News
2010English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy