Amanote Research
Register
Sign In
Estimating Power Dissipation in VLSI Circuits
IEEE Circuits and Devices Magazine
doi 10.1109/101.294740
Full Text
Open PDF
Abstract
Available in
full text
Date
July 1, 1994
Authors
F.N. Najm
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Related search
Estimation of Peak Power Dissipation in VLSI Circuits Using the Limiting Distributions of Extreme Order Statistics
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
A Survey of Power Estimation Techniques in VLSI Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Adiabatic Logic Circuits for Low Power VLSI Applications
International Journal of Science and Research (IJSR)
CMOS VLSI Design of Low Power Comparator Logic Circuits
Asian Journal of Scientific Research
Multidisciplinary
High-Level Area and Power Estimation for VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits
Active and Passive Electronic Components
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
An Algorithm for Leakage Power Reduction Through IVC in CMOS VLSI Digital Circuits
International Journal of Computer Applications
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits
Transient Time Slot (TTS) Based Run Time Leakage Reduction Method for Low Power VLSI Circuits
IOSR Journal of VLSI and Signal Processing
