Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - United States
doi 10.1109/tcad.2005.862742
Full Text
Open PDFAbstract
Available in full text
Date
October 1, 2006
Authors
Publisher
Institute of Electrical and Electronics Engineers (IEEE)