Reconfigurable and Versatile Bilrc Architecture Design With an Area and Power Efficient Technique

International Journal of Research in Engineering and Technology
doi 10.15623/ijret.2014.0319134
Full Text
Abstract

Available in full text

Date
Authors
Publisher

eSAT Publishing House

Related search

Design and Implementation of Power and Area Efficient 3-Bit Flash ADC Using GDI Technique

International Journal of Computer Applications
2018English

An Area-Efficient Design of Reconfigurable S-Box for Parallel Implementation of Block Ciphers

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2016English

An Effective Implementation of SOL’s Technique for Power and Coding Efficient VLSI Architecture in DSRC Applications

International Journal of VLSI & Signal Processing
2016English

Design of Adaptive Communication Channel Buffers for Low-Power Area-Efficient Network-On-Chip Architecture

2007English

Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture

International Journal of Intelligent Engineering and Systems
EngineeringComputer Science
2019English

An Area Efficient Thermal Energy Harvester With Reconfigurable Capacitor Charge Pump for IoT Applications

IEEE Transactions on Circuits and Systems II: Express Briefs
Electronic EngineeringElectrical
2018English

Power Efficient and Secure IPV6 Robust Header Compression Technique for Low Power Wireless Personal Area Networks

International Journal of Computer Applications
2013English

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design

2006English

Efficient Reconfigurable Design for Pricing Asian Options

ACM SIGARCH Computer Architecture News
2010English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy