Amanote Research

Amanote Research

    RegisterSign In

Virtex

doi 10.3115/991146.991206
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 1990

Authors
B. BuschbeckR. HenschelI. HöserG. KlimonowA. KüstnerI. Strake
Publisher

Association for Computational Linguistics


Related search

Level-1 Calorimeter Trigger: From Virtex-7 to UltraScale+

2019English

Real Time Morphological Image Contrast Enhancement in Virtex FPGA

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2001English

Capacitance Scaling Based Thermal Aware Design of Waveform Generator on Virtex-6

Gyancity Journal of Engineering and Technology
2018English

Voltage Scalling Based Traffic Light Controller Design on Virtex-7 FPGA Family

Gyancity Journal of Engineering and Technology
2018English

Timing Verification of Dynamically Reconfigurable Logic for the Xilinx Virtex FPGA Series

2002English

Timing Verification of Dynamically Reconfigurable Logic for the Xilinx Virtex FPGA Series

2002English

Reduction in Power Consumption of Packet Counter on VIRTEX-6 FPGA by Frequency Scaling

2017English

A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-Ii Pro Device

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2005English

Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices

International Journal of Reconfigurable Computing
HardwareArchitecture
2012English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy