Amanote Research

Amanote Research

    RegisterSign In

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

doi 10.7873/date.2013.193
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 2013

Authors
Bojan MaricJaume AbellaMateo Valero
Publisher

IEEE Conference Publications


Related search

Energy-Efficient Cache Design Using Variable-Strength Error-Correcting Codes

ACM SIGARCH Computer Architecture News
2011English

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

IEEE Computer Architecture Letters
HardwareArchitecture
2012English

Enabling Ultra Low Voltage System Operation by Tolerating On-Chip Cache Failures

2009English

An Efficient PWM Technique for Split Phase Induction Motor Operation Using Dual Voltage Source Inverters

English

Efficient Application Representation for HASTE: Hybrid Architectures With a Single, Transformable Executable

English

Design of Reliable and Efficient Flip-Flops for Subthreshold Operation Using Multi-Threshold MOSFETs and Transistor Sizing Technique

English

Reliable Cache Design With Detection of Gate Oxide Breakdown Using BIST

2009English

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

Journal of Low Power Electronics and Applications
Electronic EngineeringElectrical
2014English

Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches

IEEE Micro
HardwareElectronic EngineeringElectricalArchitectureSoftware
2003English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy