Amanote Research
Register
Sign In
Instruction Level Power Model of Microcontrollers
doi 10.1109/iscas.1999.777809
Full Text
Open PDF
Abstract
Available in
full text
Date
Unknown
Authors
C. Chakrabarti
D. Gaitonde
Publisher
IEEE
Related search
Microthreading a Model for Distributed Instruction-Level Concurrency
Parallel Processing Letters
Hardware
Theoretical Computer Science
Architecture
Software
Instruction Scheduling for Instruction Level Parallel Processors
Proceedings of the IEEE
Electronic Engineering
Electrical
Computer Science
A Study of Individualized Instruction at the College Level
Modern Language Journal
Linguistics
Language
MODELR—Model Building and Model Modification for Instruction
Behavior Research Methods
Developmental
Arts
Psychology
Educational Psychology
Cognitive Psychology
Humanities
Experimental
Software Emulation of the Architecture of Avr Microcontrollers
Scientific and Technical Volga region Bulletin
Microarchitecture Level Power and Thermal Simulation Considering Temperature Dependent Leakage Model
Empirical LTE Smartphone Power Model With DRX Operation for System Level Simulations
Microarchitecture-Level Power Management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Power Analysis Resistant AES Implementation With Instruction Set Extensions
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science