Amanote Research
Register
Sign In
On Static Compaction of Test Sequences for Synchronous Sequential Circuits
doi 10.1109/dac.1996.545575
Full Text
Open PDF
Abstract
Available in
full text
Date
Unknown
Authors
I. Pomeranz
S.M. Reddy
Publisher
ACM
Related search
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
Software
Computer Graphics
Computer-Aided Design
Electronic Engineering
Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
A Sequential Circuits Test Set Generation Method Based on Ant Colony Particle Swarmalgorithm
Robust QBF Encodings for Sequential Circuits With Applications to Verification, Debug, and Test
IEEE Transactions on Computers
Hardware
Architecture
Mathematics
Computational Theory
Theoretical Computer Science
Software
On Carrier-Frequency Gating Systems for Static Switching Circuits
IEEE Transactions on Magnetics
Electronic Engineering
Optical
Electrical
Magnetic Materials
Electronic
Estimation of the Compaction Characteristics of Soils Using the Static Compaction Method
Bulletin of the Mineral Research and Exploration
Geotechnical Engineering
Engineering Geology
Geology
Power Estimation Methods for Sequential Logic Circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Simultaneous Slack Budgeting and Retiming for Synchronous Circuits Optimization
Provably Secure Obfuscation of Diverse Watermarks for Sequential Circuits