Packet Classification Using Binary Content Addressable Memory

IEEE/ACM Transactions on Networking - United States
doi 10.1109/tnet.2016.2533613
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

High-Speed Median Filter Designs Using Shiftable Content-Addressable Memory

IEEE Transactions on Circuits and Systems for Video Technology
Electronic EngineeringMedia TechnologyElectrical
1994English

Low Power High Speed Ternary Content Addressable Memory

International Journal of Recent Technology and Engineering
EngineeringManagement of TechnologyInnovation
2019English

Design of a Content Addressable Memory-Based Parallel Processor Implementing (-1+j)-Based Binary Number System

International Journal of Advanced Computer Science and Applications
Computer Science
2014English

FPGA Implementation Content Addressable Memory in Cache Applications

International Journal of Computer Applications
2017English

Quadratic Hadamard Memories 1: Adaptive Stochastic Content-Addressable Memory

1989English

Design of Optically Coupled Three-Dimensional Content Addressable Memory

1990English

Hardware Emulation of Memristor Based Ternary Content Addressable Memory

2017English

Design and Performance Analysis of Low Power High Speed CNTFET Binary Content Addressable Memory Cell for Next Generation Communication Networks

International Journal of Innovative Technology and Exploring Engineering
Mechanics of MaterialsElectronic EngineeringCivilStructural EngineeringElectricalComputer Science
2019English

Content Addressable Memory Using Automatic Charge Balancing With Self-Control Mechanism and Master-Slave Match Line Design

Circuits and Systems
2016English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy