Amanote Research
Register
Sign In
Algorithm for Mapping Multilayer BP Networks Onto the SpiNNaker Neuromorphic Hardware
doi 10.1109/ispdc.2010.10
Full Text
Open PDF
Abstract
Available in
full text
Date
July 1, 2010
Authors
X. Jin
M. Luján
M.M. Khan
L.A. Plana
A.D. Rast
S.R. Welbourne
S.B. Furber
Publisher
IEEE
Related search
Mapping Loop Structures Onto Parametrized Hardware Pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
CMOS and Memristive Hardware for Neuromorphic Computing
Advanced Intelligent Systems
Perspective: A Review on Memristive Hardware for Neuromorphic Computation
Journal of Applied Physics
Astronomy
Physics
An Efficient Supervised Training Algorithm for Multilayer Spiking Neural Networks
PLoS ONE
Multidisciplinary
From Equations to Hardware: Towards the Systematic Mapping of Algorithms Onto Parallel Architectures
International Journal of Pattern Recognition and Artificial Intelligence
Computer Vision
Pattern Recognition
Artificial Intelligence
Software
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks
IEICE Transactions on Information and Systems
Electronic Engineering
Pattern Recognition
Hardware
Computer Vision
Electrical
Architecture
Artificial Intelligence
Software
An Unsupervised Neuromorphic Clustering Algorithm
Biological Cybernetics
Biotechnology
Computer Science
Mapping Parallel FFT Algorithm Onto SmartCell Coarse-Grained Reconfigurable Architecture
Emergent Dynamics of Neuromorphic Nanowire Networks
Scientific Reports
Multidisciplinary
