Amanote Research

Amanote Research

  • Register
  • Sign In

High Speed Low Error Floor Hardware Implementation and Fast and Accurate Error Floor Estimation of LDPC Decoders

doi 10.22215/etd/2014-10497

Full Text

Abstract

Available in

Date

Unknown

Authors

Sina Tolouei

Publisher

Carleton University


Related search

Structured LDPC Codes for High-Density Recording: Large Girth and Low Error Floor

IEEE Transactions on Magnetics
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2006English

Serial Concatenation of Reed Muller and LDPC Codes With Low Error Floor

2017English

The Analysis of Error Floor and Graphical Structure of LDPC Codes

English

Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

IEEE Transactions on Communications
Electronic EngineeringElectrical
2008English

Reduction of the Error Floor of Binary FSK by Nonlinear Frequency Discriminators

IEEE Transactions on Wireless Communications
Electronic EngineeringApplied MathematicsComputer Science ApplicationsElectrical
2003English

Error Floors of LDPC Coded BICM

2007English

Hardware-Friendly Implementation of Soft Information Set Decoders

2010English

M-Show: A System for Accurate Position Estimation in Multi-Floor Buildings

2006English

Hardware Optimized and Error Reduced Approximate Adder

Electronics (Switzerland)
ControlElectronic EngineeringSignal ProcessingComputer NetworksSystems EngineeringHardwareCommunicationsElectricalArchitecture
2019English

Amanote Research

Note-taking for researchers

Follow Amanote


© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy