Amanote Research

Amanote Research

    RegisterSign In

Algebraic Modeling of New Enhanced Linearity Threshold Comparator Based Flash ADC

IOSR Journal of VLSI and Signal Processing
doi 10.9790/4200-04621119
Full Text
Open PDF
Abstract

Available in full text

Date

January 1, 2014

Authors
Prachi PalsodkarDr. P.K Dakhole
Publisher

IOSR Journals


Related search

Linearity Enhancement Technique of Ramp Generator for ADC Testing

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2013English

Design of 8 Bit Interpolating Flash ADC Based on CMOS Technology

DEStech Transactions on Materials Science and Engineering
2017English

An 11-Bit Single-Ended SAR ADC With an Inverter-Based Comparator for Design Automation

IEICE Transactions on Electronics
Electronic EngineeringOpticalElectricalMagnetic MaterialsElectronic
2016English

A 5-Bit 5 Gs/S Flash ADC Using Multiplexer-Based Decoder

Turkish Journal of Electrical Engineering and Computer Sciences
Electronic EngineeringElectricalComputer Science
2013English

Comparator as Ip Block for Dual-Slope Adc in Integrated Circuits

Dynamics of Systems, Mechanisms and Machines
2017English

A 6-Bit 2gs/S Low Power Flash ADC

International Journal of Engineering and Technology
2012English

A 3-Bit 10-MSps Low Power CMOS Flash ADC

Communications on Applied Electronics
2018English

Analysis Method of Compound ADC Modeling

DEStech Transactions on Engineering and Technology Research
2017English

A New Metals Comparator

Chemical and Engineering News
Chemical Engineering
1949English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy