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Publications by Changkun Wu
Hardware Efficient Multiplier-Less Multi-Level 2D DWT Architecture Without Off-Chip RAM
IET Image Processing
Electronic Engineering
Signal Processing
Computer Vision
Electrical
Pattern Recognition
Software
Related publications
Power and Area Efficient Radix-8 Booth Multiplier for 2-D DWT Architecture
International Journal of Intelligent Engineering and Systems
Engineering
Computer Science
Area-Delay Efficient Flipping 2-D DWT Structure Using PEB Booth Multiplier
International Journal of Computer Applications
High Performance RISC Based 2d-DWT Architecture Implementation for Jpeg 2000
International Journal of Computer Applications
A Simplified Design of Multiplier for Multi Layer Feed Forward Hardware Neural Networks
International Journal of Research in Engineering and Technology
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
Multi-Level Texture Caching for 3D Graphics Hardware
ACM SIGARCH Computer Architecture News
Diagramming Multi-Level Service-Oriented Enterprise Architecture
SN Computer Science
On-Chip Bus Architecture Optimization for Multi-Core SoC Systems
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
An Off-Chip Input Capacitor-Less Boost Converter With Fast MPPT for Energy Harvesting
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
