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Publications by Chuan Shan
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 Nm CMOS Technology
IEEE Transactions on Circuits and Systems II: Express Briefs
Electronic Engineering
Electrical
A Reconfigurable Distributed Architecture for Clock Generation in Large Many-Core SoC
Discrete-Time Modelling and Experimental Validation of an All-Digital PLL for Clock-Generating Networks
