Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Lianly Rompis
A Logic Circuit Simulation for Finding Identical or Redundant Files Using Counter and Register
Advances in Image and Video Processing
Related publications
Deadline-Constrained Clustered Scheduling for VLIW Architectures Using Power-Gated Register Files
Transactions on Architecture and Code Optimization
Hardware
Information Systems
Architecture
Software
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
Clock-Biased Local Bit Line for High Performance Register Files
Electronics Letters
Electronic Engineering
Electrical
Preventing Integrated Circuit Piracy Using Reconfigurable Logic Barriers
TRAFIL - A Tool for Enhancing Simulation TRAce FILes Processing
Computational Comparison of Two Methods for Finding the Shortest Complete Cycle or Circuit in a Graph
RAIRO - Operations Research
Management Science
Computer Science Applications
Operations Research
Theoretical Computer Science
Finding the Right Approach for a National Underground Infrastructure Register Object
Copy Propagation Optimizations for VLIW DSP Processors With Distributed Register Files
Further Improve Circuit Partitioning Using GBAW Logic Perturbation Techniques
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software