Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by M. Madheswaran
Modified Multiply and Accumulate Unit With Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications
International Journal of Computer Applications
Related publications
Low Power Wallace and Dadda Multiplier Based on CLRCL Full Adder
IJARCCE
Incorporation of Reduced Full Adder and Half Adder Into Wallace Multiplier and Improved Carry-Save Adder for Digital FIR Filter
Circuits and Systems
Modified Booth Multiplier Using Wallace Structure and Efficient Carry Select Adder
International Journal of Computer Applications
Design and Analysis of Multi Vt and Variable Vt Based Pipelined Adder for Low Power Applications
International Journal of VLSI Design & Communication Systems
Low Power-Area Design of Full Adder Using Self Resetting Logic With GDI Technique
SSRN Electronic Journal
Low Power Adder Based ANN
International Journal of Computer Applications
Input Based Dynamic Reconfiguration for Low Power Image Processing and Secure Transmission
International Journal of Trend in Scientific Research and Development
Low-Power Adiabatic Computing With Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 Multiplier
International Journal of Recent Technology and Engineering
Engineering
Management of Technology
Innovation
CNTFET Based Highly Durable Radix-4 Multiplier Using an Efficient Hybrid Adder
Biosciences Biotechnology Research Asia
Biotechnology
Agronomy
Crop Science
Drug Discovery
