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Publications by M.D. Pant
On-Chip Decoupling Capacitor Optimization Using Architectural Level Prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Related publications
System Level Interconnect Design for Network-On-Chip Using Interconnect IPs
Research on the Cluster-Level Architectural Knowledge
International Journal of Knowledge and Systems Science
Information Systems
Organizational Behavior
Human Resource Management
Strategy
Management
Innovation
Management of Technology
Artificial Intelligence
Networks-On-Chip Architecture Customization Using Network Partitioning: A System-Level Performance Evaluation
International Journal of Computing and Digital Systems
Computer Graphics
Human-Computer Interaction
Computer Networks
Communications
Information Systems
Computer-Aided Design
Innovation
Management of Technology
Artificial Intelligence
Optimization Models for Three On-Chip Network Problems
Transactions on Architecture and Code Optimization
Hardware
Information Systems
Architecture
Software
Level Crossing in Toroidal On-Chip Microcavities
On Decoupling Points and Decoupling Zones
Production and Manufacturing Research
Industrial
Manufacturing Engineering
CVD Level Prediction Processor Using DNA Computing
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Burst-Level Congestion Control Using Hindsight Optimization
IEEE Transactions on Automatic Control
Control
Systems Engineering
Computer Science Applications
Electrical
Electronic Engineering
An Architectural Approach to Level Design
The Computer Games Journal
