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Publications by Marcelo A. Pavanello
Application of the Symmetric Doped Double-Gate Model in Circuit Simulation Containing Double-Gate Graded-Channel Transistors
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Electron Mobility in Double Gate Silicon on Insulator Transistors: Symmetric-Gate Versus Asymmetric-Gate Configuration
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Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate and Tri-Gate
Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors
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Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors
Double-Gate Fully-Depleted SOI Transistors for Low-Power High-Performance Nano-Scale Circuit Design
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Monte Carlo Simulation of Double Gate Silicon on Insulator Devices Operated as Velocity Modulation Transistors
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The Effects of Channel Doping Concentration for N-Type Junction-Less Double-Gate Poly-Si Nanostrip Transistors
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Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs
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