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Publications by Ozgur Sinanoglu
Retiming Scan Circuit to Eliminate Timing Penalty
A Novel Scan Architecture for Power-Efficient, Rapid Test
IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Computer Science Applications
Computer Graphics
Computer-Aided Design
Software
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Retiming-Based Timing Analysis With an Application to Mincut-Based Global Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Electrical
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Computer Graphics
Computer-Aided Design
Electronic Engineering
Design Optimization and Space Minimization Considering Timing and Code Size via Retiming and Unfolding
Microprocessors and Microsystems
Computer Networks
Hardware
Communications
Architecture
Artificial Intelligence
Software
Emulation of Scan Paths in Sequential Circuit Synthesis
Informatik-Fachberichte
On Minimization of Peak Power for Scan Circuit During Test
P121 to Scan or Not to Scan …again
Statistical Estimation of Circuit Timing Vulnerability Due to Leakage-Induced Power Grid Voltage Drop
Make Plans to Eliminate Cholera Outbreaks
Nature
Multidisciplinary
Multilevel Global Placement With Retiming
An Effectful Way to Eliminate Addiction to Dependence
