Amanote Research
Register
Sign In
Discover open access scientific publications
Search, annotate, share and cite publications
Publications by Sara Kamar
FPGA Implementation of RS Codec With Interleaver in DVB-T Using VHDL
International Journal of Engineering and Technology(UAE)
Architecture
Hardware
Engineering
Chemical Engineering
Biotechnology
Environmental Engineering
Computer Science
Related publications
VHDL Implementation of AES-128 on FPGA
IJIREEICE
Digital Design and Simulation of CVSD Codec Algorithm Using VHDL
International Journal of Research in Engineering and Technology
Design and Implementation of Synthesizable 32-Bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL
Nepal Journal of Science and Technology
Design and Implementation of RS (255, 223) Detecting Code in FPGA
International Journal of Computer Applications
Study of Timing Synchronization in MIMOOFDM Systems Using DVB-T
International Journal on Information Theory
Implementation of RS Encoder and RS Decoder Using UHD Architecture
International Journal of Computer Applications
Design and Implementation of Floating Point FFT Processor Using VHDL
IOSR Journal of VLSI and Signal Processing
VHDL Implementation of Nor Flash Controller
International Journal of Electronics and Communication Engineering
VHDL Implementation of GCD Processor With Built in Self Test Feature
International Journal of Computer Applications
