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Publications by Sujit R. Chhetri
Design and Implementation of Synthesizable 32-Bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL
Nepal Journal of Science and Technology
Related publications
Novel Design of 32-Bit Asynchronous (RISC) Microprocessor & Its Implementation on FPGA
International Journal of Information Engineering and Electronic Business
32-Bit MIPS RISC Processor
International Journal for Research in Applied Science and Engineering Technology
Design of FPGA Based 32-Bit Floating Point Arithmetic Unit and Verification of Its VHDL Code Using MATLAB
International Journal of Information Engineering and Electronic Business
Design and Implementation of Floating Point FFT Processor Using VHDL
IOSR Journal of VLSI and Signal Processing
Processor Design Using 32 Bit Single Precision Floating Point Unit
International Journal of Trend in Scientific Research and Development
Implementation and Design of 32 Bit Floating-Point ALU on a Hybrid FPGA-ARM Platform
A Compact FPGA Implementation of a Bit-Serial SIMD Cellular Processor Array
Design and Implementation of a Ultra-High-Speed Pipelined FFT Processor
Transactions of the Society of Instrument and Control Engineers
VHDL Implementation of AES-128 on FPGA
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