A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders

IEEE Transactions on Circuits and Systems II: Express Briefs - United States
doi 10.1109/tcsii.2016.2551550
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

Hybrid Check Node Architectures for NB-LDPC Decoders

IEEE Transactions on Circuits and Systems I: Regular Papers
Electronic EngineeringElectrical
2019English

Conditional Termination Check Min-Sum Algorithm for Efficient LDPC Decoders

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2015English

Flexible, Cost-Efficient, High-Throughput Architecture for Layered LDPC Decoders With Fully-Parallel Processing Units

2016English

Augmented Decoders for LDPC Codes

Eurasip Journal on Wireless Communications and Networking
Computer NetworksComputer Science ApplicationsSignal ProcessingCommunications
2018English

LDPC Decoders With Informed Dynamic Scheduling

IEEE Transactions on Communications
Electronic EngineeringElectrical
2010English

Extended Barrel-Shifter for Versatile QC-LDPC Decoders

IEEE Wireless Communications Letters
ControlSystems EngineeringElectronic EngineeringElectricalAstronomyPhysics
2020English

Energy-Efficient Data Representation in LDPC Decoders

Electronics Letters
Electronic EngineeringElectrical
2006English

Study of Bifurcation Behavior of LDPC Decoders

International Journal of Bifurcation and Chaos in Applied Sciences and Engineering
ModelingEngineeringMultidisciplinaryApplied MathematicsSimulation
2006English

Design of Nonbinary Quasi-Cyclic LDPC Cycle Codes

2007English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy