Amanote Research
Register
Sign In
A Novel Cell Structure With Bit Line Cap Spacer (BCS) and Top Enlarged Storage Node Contact (TESC) for 90 Nm DRAM Technology and Beyond
doi 10.7567/ssdm.2004.b-9-1
Full Text
Open PDF
Abstract
Available in
full text
Date
January 1, 2004
Authors
C.J. Yun
Y.K. Park
J.W. Lee
D.I. Bae
S.B. Kim
S.H. Shin
J.G. Lee
S.H. Lee
D.J. Lee
E.C. Lee
B.H. Roh
I.H. Nam
T.Y. Chung
Publisher
The Japan Society of Applied Physics
Related search
Novel Field Effect Diode Type Vertical Capacitorless 1t-Dram Cell With Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics
Design of Low Power SRAM Using Hierarchical Divided Bit-Line Approach in 180-Nm Technology
International Journal of Engineering Research and
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
Design and Analysis of Current Mirror OTA in 45 Nm and 90 Nm CMOS Technology for Bio-Medical Application
Bulletin of Electrical Engineering and Informatics
Control
Systems Engineering
Information Systems
Electronic Engineering
Instrumentation
Computer Networks
Hardware
Communications
Optimization
Electrical
Computer Science
Architecture
Design and Analysis of a Novel Ultra-Low Power SRAM Bit-Cell at 45nm CMOS Technology for Bio-Medical Implants
International Journal of Computer Applications
A Novel Mammalian Cell Line Development Platform Utilizing Nanofluidics and OptoElectro Positioning (OEP) Technology
Biotechnology Progress
Biotechnology
Gastrointestinal Ulcers in a Patient With a Solitary Enlarged Lymph Node
Gastroenterology
Hepatology
Gastroenterology
Body-Centered OrthorhombicC16: A Novel Topological Node-Line Semimetal
Physical Review Letters
Astronomy
Physics
Performance Comparison of 4T, 3T and 3T1D DRAM Cell Design on 32NM Technology