Amanote Research
Register
Sign In
Interconnect Enhancements for a High-Speed PLD Architecture
doi 10.1145/503049.503050
Full Text
Open PDF
Abstract
Available in
full text
Date
January 1, 2002
Authors
Michael Hutton
Sergey Shumarayev
Vinson Chan
Peter Kazarian
Victor Maruri
Tony Ngai
Jim Park
Rakesh Patel
Bruce Pedersen
Jay Schleicher
Publisher
ACM Press
Related search
Passive Time-Domain Macromodels of High Speed Interconnect Networks
Moment-Maching Analysis of High-Speed VLSI Interconnect Models.
Generalized Moment-Matching Methods for Interconnect Analysis of High-Speed VLSI Systems.
High Speed Pipelined Architecture for Adaptive Median Filter
International Journal of MC Square Scientific Research
Architecture-Level Synthesis for Automatic Interconnect Pipelining
Neural-Based Transient Behavioral Modeling of IC Buffers for High-Speed Interconnect Design
PIERS Online
Multilevel Optimization of High Speed VLSI Interconnect Networks by Decomposition.
A Distributed Control Architecture of High-Speed Networks
IEEE Transactions on Communications
Electronic Engineering
Electrical
Rsa Encryption Using Vlsi Architecture for High Speed Applications
International Journal of Advances in Signal and Image Sciences
