Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis

Transactions on Embedded Computing Systems - United States
doi 10.1145/3126564
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Association for Computing Machinery (ACM)

Related search

Design of On-Chip Testing Memory for High Speed Circuits

CVR Journal of Science & Technology
2014English

Minimizing Power Consumption of Spatial Division Based Networks-On-Chip Using Multi-Path and Frequency Reduction

2012English

High-Level Debugging and Verification for FPGA-Based Multicore Architectures

2015English

OPERON: Optical-Electrical Power-Efficient Route Synthesis for On-Chip Signals

2018English

Secure and Flexible Trace-Based Debugging of Systems-On-Chip

ACM Transactions on Design Automation of Electronic Systems
Computer Science ApplicationsElectronic EngineeringComputer GraphicsElectricalComputer-Aided Design
2017English

Stacked FSMD: A Power Efficient Micro-Architecture for High Level Synthesis

English

Dependability Evaluation of COTS Microprocessors via On-Chip Debugging Facilities

2016English

Data Reuse Driven Memory and Network-On-Chip Co-Synthesis

English

A Mechanism for Efficient Debugging of Parallel Programs

1988English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy