Amanote Research

Amanote Research

  • Register
  • Sign In

An Efficient Hardware Interleaver for 3G Turbo Decoding

doi 10.1109/rawcon.2003.1227927

Full Text

Abstract

Available in

Date

Unknown

Authors

P. AmpaduK. Kornegay

Publisher

IEEE


Related search

Efficient Decoding Technique for Block Product Turbo Codes

International Journal of Multimedia and Ubiquitous Engineering
Computer Science
2016French

Joint Interleaver Design for Multiple Turbo Codes

English

Combined Turbo Equalization and Turbo Decoding

English

High-Throughput Contention-Free Concurrent Interleaver Architecture for Multi-Standard Turbo Decoder

2011English

Parallel Interleaver Architecture With New Scheduling Scheme for High Throughput Configurable Turbo Decoder

2013English

Memory Reduced MAP Decoding for Double-Binary Turbo Decoder

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2011English

Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard

2009English

Viturbo: A Reconfigurable Architecture for Viterbi and Turbo Decoding

English

An Improved Log-Map Algorithm Based on Polynomial Regression Function for LTE Turbo Decoding

2015English

Amanote Research

Note-taking for researchers

Follow Amanote


© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy