Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - United States
doi 10.1109/tvlsi.2016.2646479
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Related search

A New Low Complexity Parallel Multiplier for a Class of Finite Fields

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2001English

A Bit-Serial Multiplier Architecture for Finite Fields Over Galois Fields

Journal of Computer Science
Computer NetworksSoftwareArtificial IntelligenceCommunications
2010English

Fast FPGA-based Pipelined Digit-Serial/Parallel Multipliers

English

Joint Design for a Hyper-Redundant Serial Manipulator

Proceedings of the Canadian Engineering Education Association (CEEA)
2011English

Parallel Intersection and Serial Composition of Finite State Transducers

1988English

Enhanced Digital Signature Using RNS Digit Exponent Representation

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2016English

Visual Search for Dimensionally Redundant Pop-Out Targets: Evidence for Parallel-Coactive Processing of Dimensions

Perception & Psychophysics
2001English

A Class of High-Precision Finite Difference Parallel Algorithms for Convection Equations

Journal of Convergence Information Technology
2011English

A Parallel Permutation Multiplier for a PGM Crypto-Chip

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
1994English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy