Amanote Research

Amanote Research

    RegisterSign In

Efficient DSP Implementation of an LDPC Decoder

doi 10.1109/icassp.2004.1326914
Full Text
Open PDF
Abstract

Available in full text

Date

Unknown

Authors
G. LechnerJ. SayirM. Rupp
Publisher

IEEE


Related search

Analysis and Implementation of Resource Efficient Probabilistic Gallager B LDPC Decoder

2017English

Parallel LDPC Decoder Implementation on GPU Based on Unbalanced Memory Coalescing

2012English

A Flexible LDPC/Turbo Decoder Architecture

Journal of Signal Processing Systems
ControlSystems EngineeringInformation SystemsSignal ProcessingSimulationHardwareArchitectureModelingTheoretical Computer Science
2010English

An Efficient FIR Filter Architecture Implementation Using Distributed Arithmetic (DA) for DSP Applications

International Journal of Innovative Technology and Exploring Engineering
Mechanics of MaterialsElectronic EngineeringCivilStructural EngineeringElectricalComputer Science
2019English

Multi-Stream LDPC Decoder on GPU of Mobile Devices

2019English

An Improved Implementation of MAX* Operation for Turbo Decoder

IEICE Electronics Express
Electronic EngineeringCondensed Matter PhysicsOpticalElectricalMagnetic MaterialsElectronic
2018English

LDPC Decoder Architecture for DVB-S2 and DVB-S2X Standards

2015English

Fpga Implementation of Linear LDPC Encoder

International Journal of Research in Engineering and Technology
2013English

LDPC Encoder and Decoder Architecture for Coding 3-Bit Message Vector

International Journal of Security and its Applications
Computer Science
2015English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy