Area & Power Optimization of Asynchronous Processor Using Xilinx ISE & Vivado

International Journal of Information Engineering and Electronic Business
doi 10.5815/ijieeb.2018.04.02
Full Text
Abstract

Available in full text

Date
Authors
Publisher

MECS Publisher

Related search

Memory, Area and Power Optimization of Digital Circuits

International Journal of Engineering Research and
2017English

Simulation and Synthesis of Heterogeneous Adder Using VIVADO

International Journal for Research in Applied Science and Engineering Technology
2018English

Gate Sizing for Constrained Delay/Power/Area Optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HardwareElectronic EngineeringElectricalArchitectureSoftware
1997English

Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization

2007English

Area Efficient Asynchronous SDM Routers Using 2-Stage Clos Switches

2012English

An Optimal LFC in Two-Area Power Systems Using a Meta-Heuristic Optimization Algorithm

International Journal of Electrical and Computer Engineering
Electronic EngineeringElectricalComputer Science
2017English

Power and Area Optimization for Multiple Restricted Multiplication

English

Modeling Services Using ISE Framework

Advances in Computer and Electrical Engineering
English

Asynchronous Simulated Kalman Filter Optimization Algorithm

International Journal of Engineering and Technology(UAE)
ArchitectureHardwareEngineeringChemical EngineeringBiotechnologyEnvironmental EngineeringComputer Science
2018English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy