Amanote Research
Register
Sign In
Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors: Design Considerations and Performance Study
IEEE Transactions on Parallel and Distributed Systems
- United States
doi 10.1109/71.850834
Full Text
Open PDF
Abstract
Available in
full text
Categories
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
Date
April 1, 2000
Authors
L. Choi
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Related search
Software Cache Coherence for Large Scale Multiprocessors
Compiler Directed Parallelization of Loops in Scale for Shared-Memory Multiprocessors
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Cache Coherence Protocols in Shared-Memory Multiprocessors
An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
Compiler-Directed Scratch Pad Memory Optimization for Embedded Multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Implementing Application-Specific Cache-Coherence Protocols in Configurable Hardware
Lecture Notes in Computer Science
Computer Science
Theoretical Computer Science
Formal Automatic Verification of Cache Coherence in Multiprocessors With Relaxed Memory Models
IEEE Transactions on Parallel and Distributed Systems
Hardware
Computational Theory
Signal Processing
Architecture
Mathematics
TSO-CC: Consistency Directed Cache Coherence for TSO
BulkSort: System Design and Parallel Hardware Implementation Considerations
International Journal of Advanced Computer Science and Applications
Computer Science
