A Method of Construction of Easily Diagnosable Logic Networks Regarding Single Faults

Keldysh Institute Preprints
doi 10.20948/prepr-2019-81
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Keldysh Institute of Applied Mathematics

Related search

Short Single Tests for Logic Networks Under Arbitrary Stuck-At Faults at Outputs of Gates

Keldysh Institute Preprints
2018English

Design of Easily Synchronizable Oscillator Networks Using the Monte Carlo Optimization Method

Physical Review E
2010English

Use of Fuzzy Logic Systems for Assessment of Primary Faults

Journal of Electrical Engineering
2015English

Logic Testing of Bridging Faults in CMOS Integrated Circuits

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
1998English

Mathematical Modeling of Arc Faults in Networks With Low Single Phase-To-Ground Fault Currents

E3S Web of Conferences
EarthEnergyPlanetary SciencesEnvironmental Science
2019English

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy

2008English

Restructuring Logic Representations With Easily Detectable Simple Disjunctive Decompositions

English

A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy

2008English

Automatic Detection of Optical “Faults” in Communications Networks

Optics and Photonics Journal
2013English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy