Amanote Research

Amanote Research

    RegisterSign In

A Reconfigurable Systolic Array SoC Design for Multicarrier Wireless Applications

doi 10.1109/mwscas.2008.4616886
Full Text
Open PDF
Abstract

Available in full text

Date

August 1, 2008

Authors
H. HoV. SzwarcT. Kwasniewski
Publisher

IEEE


Related search

A Reconfigurable Systolic Array Architecture for Multicarrier Wireless Applications

English

Design of Reconfigurable Antenna for Wireless Applications

International Journal of Engineering Research and
2016English

A Cost-Effective Reconfigurable Accelerator for Platform-Based SOC Design

English

A Franklin Array Antenna for Wireless Charging Applications

PIERS Online
2010English

Design and Implementation of T-Junction Triangular Microstrip Patch Antenna Array for Wireless Applications

International Journal of Engineering and Technology
Transfer ProcessesFluid FlowMechanical EngineeringAerospace Engineering
2016English

High Performance Systolic Array Core Architecture Design for DNA Sequencer

MATEC Web of Conferences
Materials ScienceEngineeringChemistry
2018English

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

2016English

Dynamically Reconfigurable Systolic Array Accelerators: A Case Study With Extended Kalman Filter and Discrete Wavelet Transform Algorithms

IET Computers and Digital Techniques
HardwareElectronic EngineeringElectricalArchitectureSoftware
2010English

Virtual Systolic Array for QR Decomposition

2013English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2026 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy