MAC Implementation Using Vedic Multiplication Algorithm

International Journal of Computer Applications
doi 10.5120/2522-3429
Full Text
Abstract

Available in full text

Date
Authors
Publisher

Foundation of Computer Science

Related search

Hardware Implementation of Montgomery's Modular Multiplication Algorithm

IEEE Transactions on Computers
HardwareArchitectureMathematicsComputational TheoryTheoretical Computer ScienceSoftware
1993English

Parallel Hardware Implementation of Convolution Using Vedic Mathematics

IOSR journal of VLSI and Signal Processing
2012English

Implementation of Power Efficient Vedic Multiplier

International Journal of Computer Applications
2012English

Serial Adder Based Multiplication and Accumulation Unit (Mac)

International Journal of Advances in Signal and Image Sciences
2017English

20 Tap Reconfigurable IIR Filter Using Fully Parallel MAC Algorithm

International Journal of Computer Applications
2016English

FPGA Implementation of 16-Bit Multipliers Based Upon Vedic Mathematic Approach

Jurnal Rekayasa Elektrika
2014English

Design and Implementation of High Speed 16x16 CMOS Vedic Multiplier

International Journal of Electrical, Electronics and Computers
2018English

Novel DHT Algorithm Implementation Using Sharing Multipliers

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
2014English

Vedic Svarga-

Journal of Indian and Buddhist Studies (Indogaku Bukkyogaku Kenkyu)
2011English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2024 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy