Single Precision Natural Logarithm Architecture for Hard Floating-Point and DSP-Enabled FPGAs

doi 10.1109/arith.2016.20
Full Text
Abstract

Available in full text

Date
Authors
Publisher

IEEE

Related search

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division

2014English

A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2010English

Processor Design Using 32 Bit Single Precision Floating Point Unit

International Journal of Trend in Scientific Research and Development
2018English

FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation

Journal of Computational Engineering
2014English

A Low-Powercarry Cut-Backapproximate Adder With Fixed-Point Implementation and Floating-Point Precision

2016English

A Natural Series for the Natural Logarithm

Electronic Journal of Combinatorics
CombinatoricsApplied MathematicsMathematicsGeometryDiscrete MathematicsComputational TheoryTopologyTheoretical Computer Science
2008English

An Efficient Multiple Precision Floating-Point Multiply-Add Fused Unit

Microelectronics Journal
2016English

Rpe V5: An Emulator for Reduced Floating-Point Precision in Large Numerical Simulations

Geoscientific Model Development
EarthSimulationPlanetary SciencesModeling
2017English

Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs

English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy