Amanote Research

Amanote Research

    RegisterSign In

Reconfigurable Synchronized Dataflow Processor

doi 10.1109/aspdac.2000.835062
Full Text
Open PDF
Abstract

Available in full text

Date

Unknown

Authors
H. SasakiH. MaruyamaH. KobayashiT. NakamuraH. TsukiokaN. Shoji
Publisher

IEEE


Related search

Consistency Analysis of Reconfigurable Dataflow Specifications

Lecture Notes in Computer Science
Computer ScienceTheoretical Computer Science
2002English

The Reconfigurable Arithmetic Processor

ACM SIGARCH Computer Architecture News
1988English

A High Speed Image Processor With Variable Function Reconfigurable Pipeline Processor

IEEJ Transactions on Electronics, Information and Systems
Electronic EngineeringElectrical
1992English

Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP Systems

English

Reconfigurable Multi-Butterfly Parallel Radix-R FFT Processor

Journal of Data Analysis and Information Processing
2019English

A Review on Reconfigurable Processor for Binary Image Processing.

International Journal of Advanced Research
2016English

Reconfigurable Fpga Based Soft-Core Processor for Simd Applications

Asian Journal of Pharmaceutical and Clinical Research
PharmacologyPharmaceutical Science
2017English

A Reconfigurable Optoelectronic Interconnect Technology for Multi-Processor Networks

English

Using a CSP Based Programming Model for Reconfigurable Processor Arrays

2008English

Amanote Research

Note-taking for researchers

Follow Amanote

© 2025 Amaplex Software S.P.R.L. All rights reserved.

Privacy PolicyRefund Policy