Amanote Research
Register
Sign In
Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects
doi 10.1109/ectc.2010.5490883
Full Text
Open PDF
Abstract
Available in
full text
Date
January 1, 2010
Authors
Kuan H. Lu
Suk-Kyu Ryu
Qiu Zhao
Xuefeng Zhang
Jay Im
Rui Huang
Paul S. Ho
Publisher
IEEE
Related search
Temperature Properties of the Parasitic Resistance of Through-Silicon Vias (TSVs) in High-Frequency 3-D ICs
IEICE Electronics Express
Electronic Engineering
Condensed Matter Physics
Optical
Electrical
Magnetic Materials
Electronic
Experimental Stress Characterization and Numerical Simulation for Copper Pumping Analysis of Through-Silicon Vias
IEEE Transactions on Components, Packaging and Manufacturing Technology
Electronic Engineering
Industrial
Manufacturing Engineering
Optical
Electrical
Magnetic Materials
Electronic
Synchrotron-Based Measurement of the Impact of Thermal Cycling on the Evolution of Stresses in Cu Through-Silicon Vias
Journal of Applied Physics
Astronomy
Physics
Postbond Test of Through-Silicon Vias With Resistive Open Defects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware
Electronic Engineering
Electrical
Architecture
Software
Relaxation of Thermal Stress by Dislocation Motion in Passivated Metal Interconnects
Journal of Materials Research
Mechanics of Materials
Materials Science
Condensed Matter Physics
Mechanical Engineering
Integration of Electrografted Layers for the Metallization of Deep Through Silicon Vias
Electromagnetic Analysis for Optical Coherence Tomography Based Through Silicon Vias Metrology
Applied Optics
Electronic Engineering
Molecular Physics,
Engineering
Electrical
Atomic
Optics
On Finding a Simulation Model for Carbon Nanotubes as Through-Silicon-Vias
Role of Delamination in Zeolite-Catalyzed Aromatic Alkylation: UCB-3 Versus 3-D Al-SSZ-70
ACS Catalysis
Catalysis
Chemistry