Amanote Research
Register
Sign In
An Efficient Twin-Precision Multiplier
doi 10.1109/iccd.2004.1347894
Full Text
Open PDF
Abstract
Available in
full text
Date
Unknown
Authors
M. Sjalander
H. Eriksson
P. Larsson-Edefors
Publisher
IEEE
Related search
An Efficient Two’s Complement Multiplier With FPGA Implementation
IOSR journal of VLSI and Signal Processing
An Area Efficient and High Speed Reversible Multiplier Using NS Gate
International Journal of Engineering Research and Applications
Implementation of Power Efficient Vedic Multiplier
International Journal of Computer Applications
An Energy-Efficient 32-Bit Multiplier Architecture in 90-Nm CMOS
CNTFET Based Highly Durable Radix-4 Multiplier Using an Efficient Hybrid Adder
Biosciences Biotechnology Research Asia
Biotechnology
Agronomy
Crop Science
Drug Discovery
Efficient Implementation of Multiplier for Digital FIR Filters
International Journal of Engineering Research and
An Efficient Multiple Precision Floating-Point Multiply-Add Fused Unit
Microelectronics Journal
Detuned Twin-Signal-Recycling for Ultrahigh-Precision Interferometers
Optics Letters
Optics
Atomic
Molecular Physics,
High-Precision Analysis of the Solar Twin HIP 100963
Astronomy and Astrophysics
Astrophysics
Astronomy
Planetary Science
Space