Amanote Research
Register
Sign In
Age-Aware Logic and Memory Co-Placement for RRAM-FPGAs
doi 10.1145/3061639.3062198
Full Text
Open PDF
Abstract
Available in
full text
Date
June 18, 2017
Authors
Yuan Xue
Chengmo Yang
Jingtong Hu
Publisher
ACM
Related search
Architecture-Adaptive Routability-Driven Placement for FPGAs
Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability
IEEE Transactions on Nanotechnology
Electronic Engineering
Nanotechnology
Computer Science Applications
Electrical
Nanoscience
Placement-Driven Technology Mapping for LUT-based FPGAs
Fast Timing-Driven Partitioning-Based Placement for Island Style FPGAs
Test and Diagnosis of Faulty Logic Blocks in FPGAs
IEE Proceedings - Computers and Digital Techniques
Mobility-Aware Dynamic Service Placement for Edge Computing
EAI Endorsed Transactions on Internet of Things
Placement Algorithms and Logic on Logic (Lol) 3d Integration
Journal of Mathematics and Computer Science
Computational Mechanics
Computational Mathematics
Computer Science Applications
Mathematics
QoE-aware Virtual Machine Placement for Cloud Games
Memory-To-Memory Connection Structures in FPGAs With Embedded Memory Arrays
